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| LD4000 PR4/EPR4 Read/Write Controller GENERAL DESCRIPTION The part is a high performance BICMOS read channel IC that provides all of the functions needed to implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive systems with data rates from 67 to 212 Mbps. Functional blocks include a serial port, an automatic gain control amplifier, a programmable filter, an offset canceller, a peak detecting pulse qualifier, an adaptive transversal filter, a Viterbi qualifier, a 8/9 GCR ENDEC, a data synchronizer, a time base generator, an integrating servo demodulator, as shown in figure 1. The part requires a single +5V power supply. The part utilizes an advanced BiCMOS process technology along with advanced circuit design techniques which results in a high performance device with low power consumption. FEATURES GENERAL * * * * * * * * * Register programmable data rates from 67 to 212 Mbit/s Sampled data read channel with Viterbi qualification Programmable filter for PR4 equalization Five tap transversal filter with adaptive PR4 equalization 8/9 GCR ENDEC Data Scrambler / Descrambler Presettable Precoder state Programmable write precompensation Low operating power - 1000mW maximum at 5.5V to allow use of TOFP packages. Active power management is applied to achieve this target Register programmable power management (<5 mW power down mode) 4-bit nibble and byte wide bi-directional NRZ data interface 8 bit direct write mode automatically configured for CLK=VCO/8 Serial Interface port for access to internal program storage registers Single power supply (5V 10%) Small package footprint: 100 lead TOFP AUTOMATIC GAIN CONTROL * * * * * * * * * * Dual mode AGC, continuous time during acquisition, sampled during data reads Separate AGC level storage pins for data and servo Dual rate attack and decay charge pump for rapid AGC recovery in continuous time mode Programmable, symmetric, charge pump currents for data reads in sampled mode Charge pump currents track programmable data rate during data reads Low drift AGC hold circuitry Low-Z circuitry at AGC input provides for rapid external coupling capacitor recovery AGC Amplifier squelch during Low-Z Wide bandwidth amplitude feedback circuit to allow improved stability of AGC level vs. frequency Programmable AGC controls * Separate external input pins for AGC hold, fast recovery, and Low-Z control or * Internal Low-Z and fast recovery timing for rapid transient recovery and AGC acquisition. Timing set with external resistors (2). Ultra fast decay current set with external resistor. * * * * * * version 2.1 LD4000 PR4/EPR4 Read/Write Controller FILTER / EQUALIZER * * * * * * * * * * * * Programmable, 7-pole, continuous time filter with asymmetrical zeros Channel filter and pulse slimming equalization for coarse equalization to PR4 Programmable cutoff frequency from 10 to 56 MHz Programmable boost/equalization of 0 to 13 dB Programmable "zeros" equalization provides asymmetry compensation 30% group delay variation from 0.3Fc to Fc with Fc=56 MHz Low-Z switch for fast offset recovery at the filter output No external coupling capacitors required DC offset compensation provided at the filter output Three or Five tap transversal filter for fine equalization to PR4. Self adapting symmetric Inner taps Programmable symmetric outer taps with 4 bits of resolution * Equalization hold input * Asymmetry factor output and "zeros" channel quality output DATA SEPARATOR * * * * * * * * * * * * * * * * * * * Fully integrated data separator includes data synchronizer and 8/9 GCR ENDEC Register programmable to 212 Mbps Fast Acquisition, sampled data phase locked loop Decision directed clock recovery from data samples Adaptive clock recovery thresholds Programmable damping ratio for data synchronizer PLL is constant for all data rates Data scrambler / descrambler to reduce fixed pattern effects Byte wide NRZ data interface and 4 bits nibble interface Time base tracking, programmable write precompensation Differential PECL write data output Surface defect scan mode Direct Write modes SERVO 6-burst servo capture with A-B, C-D, E-F outputs Internal hold capacitors Separate, automatically selected, registers for servo fc, boost, and threshold Wide bandwidth, high precision full-wave rectifier is optimized for low-level linearity "Soft Landing" charge pump architecture Programmable selection of normal or differentiated filter output to servo-capture block Programmable gain with 2 external inputs PULSE QUALIFICATION * * * * Sampled Viterbi qualification of signal equalized to PR4 Register programmable hysteresis or window qualification peak detector for servo reads, with programmable thresholds Selectable RDS pulse width for servo grey code reads RDS and PPOL outputs are disabled during burst capture to reduce noise generation TIME BASE GENERATOR * * * * Better than 1% frequency resolution Up to 225 MHz frequency output Independent M and N divide-by registers No active external components required Page 2 version 2.1 VPF VPT TPA TPB RDS/RDSB VNF VNT TPE VPS VPS VPP VPA EQHOLD VNC VND VNS VNS VNP VNA TPAB TPBB VPC VPD VRDT PPOL TPDB TPCB TPD TPC RX 88 SP 89 90 91 87 84 85 60 66 65 64 63 8 69 67 55 54 14 18 37 86 62 68 58 47 12 15 38 95 96 TPC MUX TPE MUX TEST POINT MUX LOWZ UFDC FASTREC SFWR TPD MUX VIA CN SP 98 OD+ CP 30 SBDB OD- VIAB DP DN To SFC 97 AGC AMP DC OFFSET CANCEL LEVEL OR HYSTERISIS PULSE QUAL ON+ DUAL "OR" TYPE SYNC BYTE DETECTOR PROGRAMMABLE 7th ORDER LOW-PASS FILTER ASYMMETRIC 0's ON- 31 PERR/NCLK PARITY GEN/CHK EN SFC LOWZ SP CHANQUAL 32 NRZP SP 33-36, 39-42 VITERBI DETECTOR MUX DESCRAMBLER DSCLK CWBD SQUELCH SSBYP SP DSCLK SP ASYMM FACTOR SP SERIAL TO PARALLEL 9/8 (0,4/4) DECODER CODE WORD BOUNDARY DETECTOR 8/9 (0,4/4) ENCODER SCRAMBLER PARALLEL INTERFACE 43 NRZ0-7 BYPS 4 VMIN 5-TAP EQUALIZER 2-ADAPTIVE 2-PROG WCLK BYPD 3 SG NIBBLE INTERFACE HOLDB FROM LEVEL QUAL 5 SFC HOLD AGCRST SYNC FIELD COUNTER 92 UFDC RCLK VCC SFC AUTOMATIC TRAINING & SYNC BYTE GENERATOR SERVO 19 20 DWB DW Page 3 FULL WAVE RECTIFIER MUX PARALLEL TO SERIAL FULL WAVE RECTIFIER PRECODER SP SAMPLED AGC CHARGE PUMP CONV AGC CHARGE PUMP DAC SP 21 MUX VCO SYNC PATTERN GEN SMS WRITE PRECOMP MUX WRITE FLIP-FLOP 22 WDB WD 45 SP SFWR TBGOUT SP LOWZ 6 HOLD SP DWRB 7 FASTREC FASTREC WRDEL E 94 AGC CONTROL LOGIC LOWZ + - SQUELCH DATA SYNCHRONIZER AGCDEL C 93 UFDC DECISION DIRECTED PHASE DETECTOR SP SFC CWBD VREF A 73 SP VREF SERVO LEAKAGE CHARGE PUMP PHASE/ FREQ DETECTOR VCO DSCLK TBGOUT RCLK CLOCK GEN RCLK 44 RCLK SDEN 11 TBGOUT SCLK 9 DAMPING CONTROL CHANQUAL ASYMM FACTOR VREFS DACs TIME BASE GENERATOR SP SP 61 ATO SP SDATA 10 SERIAL PORT & CONTROL REGISTERS VREFS DECODE LOGIC ATO TEST MUX SG SP 83 1/(M+1) 1/(N+1) RG 29 WG 28 CONTROL LOGIC PHASE/ FREQ DETECTOR CHARGE PUMP VCO POWER DOWN CONTROL SP 69 71 77 78 82 81 80 79 13 72 16 17 57 56 46 70 RR E-F C-D A-B N/X AV1 AV0 FREF PDWNB FLTR1B FLTR1 VREFS FLTR2B FLTR2 RESETB STROBE LD4000 PR4/EPR4 Read/Write Controller version 2.1 Fig 1 LD4000 Block Diagram LD4000 PR4/EPR4 Read/Write Controller 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 N/C N/C VIA VIAB RX VPA WRDEL AGCDEL AGCRST TPCB TPC TPDB TPD TPE VNA PPOL RDS/RDSB SG N/X A-B C-D E-F AV1 AV0 N/C 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 N/C N/C WG/WGB RG SBDB PERR NRZP NRZ0 NRZ1 NRZ2 NRZ3 VND VPD NRZ4 NRZ5 NRZ6 NRZ7 WCLK RCLK DWRB PDWNB VPC N/C N/C N/C 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 N/C N/C BYPD BYPS HOLDB LOWZ FASTREC VRDT SCLK SDATA SDEN VPF FREF VNF VPT FLTR1 FLTR1B VNT DW1B DW1 WDB WD N/C N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 N/C N/C VREF RR VREFS RESETB STROBE VPS VNS TPA TPAB TPB TPBB VPS ATO EQHOLD VNS VPP FLTR2 FLTR2B VNP VNC N/C N/C N/C LD4000 100-Lead TQFP Page 54 version 2.1 |
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